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ddr_cntl_a_withtb
- arm控制FPGA的DDR测试代码，共享一下-arm control FPGA DDR test code sharing what
tstSdram
- pnx1500 ddr test demo
leon3-altera-ep2s60-ddr
- This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOT
ddrsdram_verilog
- 内附doc是DDR SDRAM 参考设计文档；model包含SDRAM Verilog的模型；simulation包含verilog测试平台、modelsim工程文、设计库函数；source包含verilog源文件；synthesis包含工程的综合文件 。-Enclosing the doc is a DDR SDRAM reference design documentation model contains SDRAM Verilog model simulation with veri
ddr
- 合众达DM6446试验箱学习实验源代码 ddr内存实验-the experimental source code DM6446 chamber ddr memory test
DDR_SDRAM_controller
- DDR SDRAM控制器的VHDL源代码，含详细设计文档。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides t
Hardware_Test_Programs
- ccs下对dm6446的测试程序，能够检测ddr,nandflash,uart,usb等硬件电路的裸板测试代码，包含库文件，板级gel文件，开发环境在TI ccs3.3下。-ccs on DM6446 testing procedures can detect ddr, nandflash, uart, usb hardware such as the bare circuit board to test the code, including library files, board-leve
DDRSDRAMControllerverilogcode
- 这个设计是使用Virtex-4实现DDR的控制器的，设计分为三个主要模块：Front-End FIFOs,DDR SDRAM Controller和Datapath Module。其中主要是DDR SDRAM Controller,当然还有测试模块。-This design is the use of Virtex-4 implementation of the DDR controller, the design is divided into three main modules: Fron
DDRSDRAM_VHDL
- 内附doc是DDR SDRAM 参考设计文档；model包含SDRAM VHDL的模型；simulation包含VHDL测试平台、modelsim工程文、设计 库函数；source包含vhdl源文件；synthesis包含工程的综合文件。-Enclosing the doc is a DDR SDRAM reference design documentation model contains SDRAM VHDL model simulation with VHDL test benc
ddr_contrl
- DDR controller source code and test bench in VerilogHDL. It is very useful to develop DDR project.-DDR controller source code and test bench in VerilogHDL.
ddr2_controller
- DDR2控制器设计原码,可以在FPGA上测试通过,并对外部的ddr memory进行读写访问.-DDR2 controller design of the original code, can be tested through the FPGA, and external ddr memory read and write access.
ddr
- 测试DDR内存，Linux下编译运行-Test Demos under CCS\tests\ddr
ddr
- 该程序是TI的达芬奇处理器DM6467开发板的DDR测试程序，该程序的开发环境是CCS3.3，使用的编程语言是C-The program is for TI s DaVinci processor DM6467 development board test program of DDR , the program s development environment is CCS3.3, using the programming language is C
ddr
- 在TMS320DM6446 DSP环境下对DDR2进行读写测试-In TMS320DM6446 DSP environment, read and write test on the DDR2
TEST-BENCH.vhd
- test bench for ddr 1
DM365-ddr-test-and-debug-programs
- DM365的ddr测试和板子调试程序，最后调试顺利通过-DM365 ddr test and debug programs and at last successful
ddr
- 达芬奇系列开发板，ddr测试程序，用于检测Dsp和ddr之间的通路正常工作-Da Vinci series development board, DDR test program, used to detect between Dsp and DDR pathways to work normally
test
- test ddr to ddr performance
ddr
- DM36x平台下的DDR测试程序（c源码），包括对DDR的写入和读出。(The DDR test program (c source code) under the DM36x platform, including the writing and reading of the DDR.)
ddr_stress_tester_v2.70
- DDR 压力测试 ，针对imx6平台的DDR压力测试工具(DDR test for imx6 platform)